Intel’s research teams have unveiled work that the company believes will help it accelerate and shrink computing systems over the next 10 years, with several technologies designed to stack parts of the systems on top of each other.
Intel Research Components Group presented the results of their work in articles at an international conference in San Francisco.
The Silicon Valley company is looking to regain its lead in manufacturing the smallest and fastest chips it has lost to rivals such as Taiwan Semiconductor Manufacturing Co (TSMC) and Samsung Electronics in recent years.
While Intel CEO Pat Gelsinger unveiled commercial plans to regain that lead by 2025, research work revealed on Saturday shows how Intel plans to compete beyond 2025.
One of the ways Intel packs more processing power into chips is by arranging “tiles” or “chiplets” in three dimensions, rather than creating the chips as one two-dimensional piece.
Intel has shown work that can allow 10 times more connections between stacked tiles, meaning that more complex tiles can be stacked on top of each other.
But perhaps the biggest breakthrough shown was a research paper demonstrating a way to stack transistors — tiny switches that form the most basic building blocks, representing the 1s and 0s of digital logic — on top of one another.
Intel believes the technology will provide a 30% to 50% increase in the number of transistors it can pack into a given area of a chip.
Increasing the number of transistors is the main reason chips have been consistently getting faster over the past 50 years.
“By stacking the devices directly on top of each other, we are clearly saving area,” said Paul Fischer, director and senior engineer at Intel’s Component Research Group, in an interview with Reuters.
“We’re reducing interconnect lengths and actually saving energy, making it not only more economical, but also better performing.
